Memory device and system including the same

ABSTRACT

A memory device includes a lower structure, a stacked structure on the lower structure, the stacked structure including horizontal layers and interlayer insulating layers alternately stacked in a vertical direction, and each of the horizontal layers including a gate electrode, a vertical structure penetrating through the stacked structure in the vertical direction, the vertical structure having a core region, a pad pattern with a pad metal pattern on the core region, a dielectric structure including a first portion facing a side surface of the core region, a second portion facing at least a portion of a side surface of the pad metal pattern, and a data storage layer, and a channel layer between the dielectric structure and the core region, a contact structure on the vertical structure, and a conductive line on the contact structure.

CROSS-REFERENCE TO RELATED APPLICATION

Korean Patent Application No. 10-2020-0073654, filed on Jun. 17, 2020,in the Korean Intellectual Property Office, and entitled: “Memory Deviceand System Including the Same,” is incorporated by reference herein inits entirety.

BACKGROUND 1. Field

Embodiments relate to a memory device and a system including the same.

2. Description of the Related Art

As demand for high performance, high speed and/or multifunctionality ofsemiconductor devices increases, the degree of integration of memorydevices increases. To increase the degree of integration of a memorydevice, instead of disposing the gates on a two-dimensional plane, amethod of disposing gates in a vertical direction has been proposed.

SUMMARY

According to example embodiments, a memory device includes a lowerstructure, a stacked structure including horizontal layers andinterlayer insulating layers alternately stacked on the lower structurein a vertical direction, a vertical structure penetrating through thestacked structure in the vertical direction, a contact structuredisposed on the vertical structure, and a conductive line disposed onthe contact structure. Each of the horizontal layers includes a gateelectrode, the vertical structure includes a core region, a pad patternincluding a pad metal pattern, on the core region, a dielectricstructure including a first portion facing a side surface of the coreregion and a second portion facing at least a portion of a side surfaceof the pad metal pattern, and a channel layer between the dielectricstructure and the core region, and the dielectric structure includes adata storage layer.

According to example embodiments, a memory device includes a lowerstructure, a stacked structure on the lower structure, the stackedstructure including gate layers and interlayer insulating layersalternately stacked in a vertical direction, and gate pads extendingfrom the gate layers and arranged in a stepped shape, a first verticalstructure penetrating through the stacked structure in a verticaldirection, perpendicular to an upper surface of the lower structure, afirst contact structure on the first vertical structure, gate contactstructures on the gate pads, a peripheral contact structure spaced apartfrom the gate layers, a conductive line on the first contact structure,and gate connection wirings on the gate contact structures. The firstcontact structure includes a first lower contact plug contacting thefirst vertical structure, and a first upper contact plug disposed on thefirst lower contact plug and contacting the first lower contact plug.The first vertical structure includes a core region, a dielectricstructure including a data storage layer, on a side surface of the coreregion, a pad metal pattern on the core region, and a semiconductorlayer facing at least a portion of a side surface of the pad metalpattern.

According to example embodiments, a system includes a memory device, anda controller device electrically connected to the memory device. Thememory device includes a lower structure, a stacked structure on thelower structure, the stacked structure including gate layers andinterlayer insulating layers alternately stacked in a verticaldirection, and gate pads extending from the gate layers and arranged ina stepped shape, a vertical structure penetrating through the stackedstructure in a vertical direction, perpendicular to an upper surface ofthe lower structure, a first contact structure on the first verticalstructure, gate contact structures on the gate pads, a second contactstructure spaced apart from the gate layers and the vertical structure,a conductive line on the first contact structure, gate connectionwirings on the gate contact structures, and a peripheral connectionwiring on the second contact structure. The first contact structureincludes a first lower contact plug contacting a pad pattern, and afirst upper contact plug disposed on the first lower contact plug andcontacting the first lower contact plug. The vertical structure includesa core region, a dielectric structure including a data storage layer, ona side surface of the core region, a pad metal pattern on the coreregion, and a semiconductor layer facing at least a portion of a sidesurface of the pad metal pattern.

BRIEF DESCRIPTION OF DRAWINGS

Features will become apparent to those of skill in the art by describingin detail exemplary embodiments with reference to the attached drawings,in which:

FIG. 1 is a schematic diagram of a system including a memory deviceaccording to an example embodiment;

FIGS. 2A and 2B are cross-sectional views illustrating a memory deviceaccording to an example embodiment;

FIGS. 2C and 3 are partially enlarged cross-sectional views of FIG. 2B;

FIG. 4 is a partially enlarged cross-sectional view of FIG. 3;

FIG. 5 is a plan view illustrating a portion of a memory deviceaccording to an example embodiment;

FIG. 6 is a partially enlarged cross-sectional view illustrating amodified example of a memory device according to an example embodiment;

FIGS. 7A to 7E are partially enlarged cross-sectional views illustratinga modified example of a memory device according to an exampleembodiment;

FIG. 8 is a partially enlarged cross-sectional view illustrating amodified example of a memory device according to an example embodiment;

FIG. 9 is a cross-sectional view illustrating a memory device accordingto an example embodiment;

FIGS. 10A to 13B are cross-sectional views illustrating an example of amethod of forming a memory device according to an example embodiment;and

FIGS. 14A to 15B are cross-sectional views illustrating another exampleof a method of forming a memory device according to an exampleembodiment.

DETAILED DESCRIPTION

FIG. 1 is a schematic diagram of a system including a memory deviceaccording to an example embodiment.

Referring to FIG. 1, in an example embodiment, a system 1 may include amemory device 10 according to an example embodiment, and a controllerdevice 60 electrically connected to the memory device 10 through aconnection structure 70. The system 1 may be a data storage system. Inan example, the connection structure 70 may be, e.g., a printed circuitboard or a board on which a plurality of packages are mounted.

In an example, the memory device 10 may be a non-volatile memory device.For example, the memory device 10 may be a NAND flash memory device, butembodiments are not limited thereto. For example, the memory device 10may be a variable resistance memory device that stores information usinga change in resistance.

In an example, the memory device 10 may be a component of the system 1formed in the form of a semiconductor package. The memory device 10 maybe a single semiconductor chip or a semiconductor package includingstacked semiconductor chips. In this case, each of the stackedsemiconductor chips may be a nonvolatile memory device, e.g., a NANDflash memory device.

In an example, the controller device 60 may be formed as anothersemiconductor package spaced apart from the memory device 10 formed inthe form of a semiconductor package. In another example, the controllerdevice 60 may be included in a single semiconductor package, togetherwith the memory device 10.

In an example, the controller device 60 may be electrically connected tothe memory device 10 to control operations of the memory device 10. Forexample, the controller device 60 may exchange commands and/or data withthe memory device 10.

In an example, the system 1 may be a data storage device, e.g., a solidstate drive (SSD). In another example, the system 1 may be an electronicdevice including a storage device and a display device.

The memory device 10 may include a bit line BL, a common source lineCSL, word lines WL, upper gate lines UL1 and UL2, lower gate lines LL1and LL2, and a cell string CSTR between the bit line BL and the commonsource line CSL. The cell string CSTR may include one or more lowertransistors LT1 and LT2 adjacent to the common source line CSL, one ormore upper transistors UT1 and UT2 adjacent to the bit line BL, and aplurality of memory cell transistors MCT disposed between the one ormore lower transistors LT1 and LT2 and the one or more upper transistorsUT1 and UT2.

The one or more lower transistors LT1 and LT2, the plurality of memorycell transistors MCT, and the one or more upper transistors UT1 and UT2may be connected in series. In an example, the one or more uppertransistors UT1 and UT2 may include a string selection transistor, andthe one or more lower transistors LT1 and LT2 may include a groundselection transistor.

In an example, the one or plurality of lower transistors LT1 and LT2 maybe provided in plural, and the plurality of lower transistors LT1 andLT2 may include a lower erase control transistor LT1 and a groundselection transistor LT2 connected in series. The ground selectiontransistor LT2 may be disposed on the lower erase control transistorLT1.

In an example, the one or more upper transistors UT1 and UT2 may beprovided in plural, and the plurality of upper transistors UT1 and UT2may include a string selection transistor UT1 and an upper erase controltransistor UT2 connected in series. The upper erase control transistorUT2 may be disposed on the string selection transistor UT1.

The lower gate lines LL1 and LL2 may include a first lower gate line LL1and a second lower gate line LL2, and the upper gate lines UL1 and UL2may include a first upper gate line UL1 and the second upper gate lineUL2. The first lower gate line LL1 may be a gate electrode of the lowererase transistor LT1, and the second lower gate line LL2 may be a gateelectrode of the ground selection transistor LT1. The word Lines WL maybe gate electrodes of the memory cell transistors MCT, and the firstupper gate line UL1 may be a gate electrode of the string selectiontransistor UT1, and the second upper gate line UL2 may be a gateelectrode of the upper erase transistor UT2.

An erase operation of erasing data stored in the memory cell transistorsMCT may use a gate induced drain leakage (GIDL) phenomenon occurring inthe lower and upper erase transistors LT1 and UT2. For example, holesgenerated by the GIDL phenomenon in the lower and upper erasetransistors LT1 and UT2 are injected into the channels of the memorycell transistors MCT, and the data of the memory cell transistors MCTmay be erased by the holes injected into the channels of the celltransistors MCT. For example, holes injected into the channels of thememory cell transistors MCT may enable electrons trapped in the datastorage layer of the memory cell transistors MCT to escape to thechannels of the memory cell transistors MCT.

In the memory device 10, a plurality of cell strings CSTR may bearranged. An area in which the plurality of cell strings CSTR arearranged may be defined as a memory cell array area 20. In the memorydevice 10, a plurality of cell strings CSTR may be electricallyconnected to one bit line BL, and the bit line BL that is electricallyconnected to the plurality of cell strings CSTR as described above maybe disposed in plural.

The memory device 10 may further include a peripheral circuit area 40. Aperipheral circuit of the peripheral circuit area 40 may include a rowdecoder 46, a page buffer 42, and a column decoder 44.

The word lines WL, the upper gate lines UL1 and UL2, and the lower gatelines LL1 and LL2 may extend from the memory cell array area 20 to agate connection area 30 adjacent to the memory cell array area 20, andmay include gate pads arranged in a stepped shape in the gate connectionarea 30. The memory cell transistors MCT may be electrically connectedto the row decoder 46 through the word lines WL, the upper gate linesUL1 and UL2, and the lower gate lines LL1 and LL2, and may be connectedto the page buffer 42 and the column decoder 44 through the bit line BL.

The connection structure 70 may be electrically connected to the memorydevice 10 by a connection line 55 connected to the peripheral circuitarea 40 in the memory device 10.

Next, the memory device 10 according to an example embodiment will bedescribed in more detail with reference to FIGS. 2A to 2C. FIG. 2Aillustrates a cross-sectional structure of a portion of the memory cellarray area 20 cut in the Y direction in the memory device 10 describedwith reference to FIG. 1. FIG. 2B is a cross-sectional view of the gateconnection area 30 and a portion of the memory cell array area 20 in theX direction perpendicular to the Y direction, in the memory device 10described with reference to FIG. 1. FIG. 2C is an enlarged view ofportion “A” in FIG. 2B.

First, with reference to FIGS. 1 and 2A, a cross-sectional structure ofa portion of the memory cell array area 20 cut in the Y direction in thememory device 10 described with reference to FIG. 1 will be described.

Referring to FIGS. 1 and 2A, the memory device 10 may include a lowerstructure 102, a stacked structure 130 s on the lower structure 102,vertical structures 142 penetrating through the stacked structure 130 s,and a conductive line 196 a on the vertical structures 142. In anexample, the conductive line 196 a may be the bit line BL described withreference to FIG. 1.

The lower structure 102 may include a substrate 104, a peripheralcircuit 108 on the substrate 104, a lower insulating layer 110 coveringthe peripheral circuit 108, a pattern structure 112 disposed on thelower insulating layer 110 and having a first opening 115 a, and a firstgap-fill insulating layer 127 g 1 filling the first opening 115 a.

The substrate 104 may be a semiconductor substrate that may be formed ofa semiconductor material, e.g., silicon or the like. The peripheralcircuit 108 may include the row decoder 46, the page buffer 42, and thecolumn decoder 44 described with reference to FIG. 1. The peripheralcircuit 108 may include a peripheral transistor including a peripheralgate 108 g and a peripheral source/drain 108 s, and a peripheral wiring108 w. The peripheral wiring 108 w may include peripheral pads, e.g., afirst peripheral pad 108 p 1.

The peripheral gate 108 g may be formed on an active region 106 adefined by a device isolation layer 106 s formed in the substrate 104.The peripheral source/drain 108 s may be formed in the active region 106a on both sides of the peripheral gate 108 g. The lower insulating layer110 may cover the peripheral circuit 108.

The pattern structure 112 may include a pattern layer 115. The patternlayer 115 may be a silicon layer. At least a portion of the patternlayer 115 may be a silicon layer having N-type conductivity.

In an example, the pattern structure 112 may include a horizontalconnection layer 118 that may be disposed on the pattern layer 115 tocontact the pattern layer 115. In an example, the horizontal connectionlayer 118 may include a lower horizontal connection layer 122 and anupper horizontal connection layer 124 that may be disposed on the lowerhorizontal connection layer 122 to contact the lower horizontalconnection layer 122.

At least one of the lower horizontal connection layer 122 and the upperhorizontal connection layer 124 may include a doped silicon layer. Forexample, the lower horizontal connection layer 122 and the upperhorizontal connection layer 124 may include a silicon layer havingN-type conductivity. In another example, the doped silicon layer may bereplaced with a doped germanium layer or a doped silicon-germaniumlayer.

The stacked structure 130 s may include horizontal layers 137 andinterlayer insulating layers 133 alternately and repeatedly stacked onthe lower structure 102. Among the horizontal layers 137 and theinterlayer insulating layers 133, a lowermost layer and an uppermostlayer may be interlayer insulating layers. An uppermost interlayerinsulating layer 133U among the interlayer insulating layers 133 mayhave a thickness greater than that of each of the other interlayerinsulating layers. The interlayer insulating layers 133 may be formedof, e.g., silicon oxide.

The vertical structures 142 may be disposed in channel holes 140penetrating through the stacked structure 130 s in the verticaldirection Z. The vertical direction Z may be a direction perpendicularto the upper surface of the lower structure 102.

Each of the vertical structures 142 may include a dielectric structure144, a channel layer 153, a core region 156, and a pad pattern 160. Thepad pattern 160 may be disposed on the core region 156. At least aportion of the channel layer 153 may be disposed on a side surface ofthe core region 156 and a side surface of the pad pattern 160. Thedielectric structure 144 may cover an outer side surface and a bottomsurface of the channel layer 153. In an example, the vertical structures142 may penetrate through the stacked structure 130 s and extenddownwardly to penetrate through the horizontal connection layer 118 andextend into the pattern layer 115.

In an example, the channel layer 153 may further include a portioncovering the bottom surface of the core region 156, and the dielectricstructure 144 may include a portion covering the bottom surface of thechannel layer 153. In an example, the lower horizontal connection layer122 of the horizontal connection layer 118 may penetrate through thedielectric structure 144 and may contact the channel layer 153, and aportion of the dielectric structure 144 and an extended portion of thelower horizontal connection layer 122 may be interposed between theupper horizontal connection layer 124 and the channel layer 153.

In an example, the memory device 10 may further include a first upperinsulating layer 173, a second upper insulating layer 180, and a thirdupper insulating layer 186 that are sequentially stacked on the stackedstructure 130 s. In an example, the memory device 10 may further includea trench 176 (FIG. 11A) penetrating through the first upper insulatinglayer 173, the stacked structure 130 s, and the horizontal connectionlayer 118, and a separation structure 178 within the trench 176.

In an example, the separation structure 178 may include a firstseparation pattern 178_1 and a second separation pattern 178_2. Thefirst separation pattern 178_1 may be disposed on a side surface of thesecond separation pattern 178_2.

In an example, the first and second separation patterns 178_1 and 178_2may be formed of an insulating material. In another example, the firstseparation pattern 178_1 may be formed of an insulating material, andthe second separation pattern 178_2 may include a conductive material(e.g., doped polysilicon, metal nitride, a metal-semiconductor compound,a metal, or the like).

In an example, the memory device 10 may further include a firstinsulating region 130 i_1 defined in a partial region of the stackedstructure 130 s. The first insulating region 130 i_1 may overlap thefirst gap-fill insulating layer 127 g 1.

In an example, the first insulating region 130 i_1 may includeinsulating layers 136 a positioned at substantially the same heightlevel as the horizontal layers 137 of the stacked structure 130 s, andinsulating portions 133 i adjacent to the insulating layers 136 a in thevertical direction Z and extending from the interlayer insulating layers133. In another example, the first insulating region 130 i_1 may also beformed of a columnar insulating pattern.

In an example, the memory device 10 may further include bit line contactstructures 192 a and first peripheral contact structures 192 b. Each ofthe bit line contact structures 192 a may include a lower bit linecontact plug 184 a and an upper bit line contact plug 188 a. The firstperipheral contact structure 192 b may include a first peripheral lowercontact plug 184 b and a first peripheral upper contact plug 188 b.

In each of the bit line contact structures 192 a, the lower bit linecontact plug 184 a penetrates through the first and second upperinsulating layers 173 and 180, and may be electrically connected to thevertical structures 142, respectively, and the upper bit line contactplug 188 a may penetrate through the third upper insulating layer 186and may be electrically connected to the lower bit line contact plug 184a.

The first peripheral lower contact plug 184 b extends into the lowerinsulating layer 110, while penetrating through the first and secondupper insulating layers 173 and 180, the first insulating region 130i_1, and the first gap-fill insulating layer 127 g 1, and may beelectrically connected to the first peripheral pad 108 p 1 of theperipheral wiring 108 w. The first peripheral upper contact plug 188 bmay penetrate through the third upper insulating layer 186 and may beelectrically connected to the first peripheral lower contact plug 184 b.The conductive line 196 a, which may be a bit line (BL of FIG. 1), maybe electrically connected to the bit line contact structures 192 a andthe first peripheral contact structures 192 b.

Next, referring to FIGS. 1, 2B and 2C, a cross-sectional structure of aportion of the memory cell array area 20, and the gate connection area30, cut in the X direction in the memory device 10 described withreference to FIG. 1, will be described.

Referring to FIGS. 1, 2B and 2C, in an example, the horizontalconnection layer 118 may further include an intermediate structure 120.The intermediate structure 120 may include a first layer 120 a 1, asecond layer 120 a 2, and a third layer 120 a 3 that are sequentiallystacked. The first and third layers 120 a 1 and 120 a 3 may include,e.g., silicon oxide. The second layer 120 a 2 may include, e.g., siliconnitride or silicon oxide. The upper horizontal connection layer 124 maycover the lower horizontal connection layer 122 and the intermediatestructure 120.

In an example, in a boundary region between the memory cell array area20 and the gate connection area 30, the intermediate structure 120 andthe lower horizontal connection layer 122 may be spaced apart from eachother. Between the intermediate structure 120 and the lower horizontalconnection layer 122 spaced apart from each other, the upper horizontalconnection layer 124 may contact the pattern layer 115.

In an example, the intermediate structure 120 may include portionsspaced apart from each other in a region not overlapping with thestacked structure 130 s, and between the portions of the intermediatestructure 120 spaced apart from each other, and between the intermediatestructure 120 and the lower horizontal connection layer 122 spaced apartfrom each other, the upper horizontal connection layer 124 may contactthe pattern layer 115.

In an example, the pattern structure 112 may have a second opening 115b. In an example, the memory device 10 may further include a secondgap-fill insulating layer 127 g 2 filling the second opening 115 b, andan intermediate insulating layer 127 on an outer side surface of thepattern structure 112.

The stacked structure 130 s may extend from the memory cell array area20 into the gate connection area 30. In the stacked structure 130 s, thehorizontal layers 137 and the interlayer insulating layers 133 mayextend from the memory cell array area 20 into the gate connection area30. In the gate connection area 30, the stacked structure 130 s mayinclude gate pads GP arranged in a stepped shape in the gate connectionarea 30. The stepped shape in which the gate pads GP are arranged is notlimited to the shape illustrated in FIG. 2B and may be modified invarious shapes.

In an example, the memory device 10 may further include a cappinginsulating layer 139 having an upper surface substantially coplanar withthe upper surface of the uppermost interlayer insulating layer 133U. Thecapping insulating layer 139 may be formed of, e.g., silicon oxide. Thefirst to third upper insulating layers 173, 180 and 186 described withreference to FIG. 2A may be sequentially stacked on the stackedstructure 130 s and the capping insulating layer 139.

In an example, the memory device 10 may further include a secondinsulating region 130 i_2 defined in a partial region of the stackedstructure 130 s. The second insulating region 130 i_2 may overlap thesecond gap-fill insulating layer 127 g 2.

In an example, the second insulating region 130 i_2 includes insulatinglayers 136 a positioned at substantially the same height level as thehorizontal layers 137 of the stacked structure 130 s in the gateconnection area 30, and insulating portions 133 i adjacent to theinsulating layers 136 a in the vertical direction Z and extending fromthe interlayer insulating layers 133. In another example, the secondinsulating region 130 i_2 may be formed in a columnar insulatingpattern.

In an example, the memory device 10 may further include gate peripheralcontact structures 192 c, a second peripheral contact structure 192 d, athird peripheral contact structure 192 e, and a fourth peripheralcontact structure 192 f Each of the gate peripheral contact structures192 c may include a lower gate contact plug 184 c and an upper gatecontact plug 188 c sequentially stacked. The second peripheral contactstructure 192 d may include a second peripheral lower contact plug 184 dand a second peripheral upper contact plug 188 d sequentially stacked.The third peripheral contact structure 192 e may include a thirdperipheral lower contact plug 184 e and a third peripheral upper contactplug 188 e that are sequentially stacked. The fourth peripheral contactstructure 192 f may include a fourth peripheral lower contact plug 184 fand a fourth peripheral upper contact plug 188 f sequentially stacked.

The lower bit line contact plugs 184 a, the first peripheral lowercontact plug 184 b, the lower gate contact plugs 184 c, the secondperipheral lower contact plug 184 d, the third peripheral lower contactplug 184 e, and the fourth peripheral lower contact plug 184 f may haveupper surfaces positioned at the same height level.

The lower gate contact plugs 184 c are in contact with and electricallyconnected to the gate pads GP, and extend upwardly to penetrate throughthe capping insulating layer 139 and the first and second upperinsulating layers 173 and 180. The second peripheral lower contact plug184 d is in contact with and electrically connected to a secondperipheral pad 108 p 2 of the peripheral wiring 180 w, and extendsupwardly to penetrate through the second insulating region 130 i_2, thecapping insulating layer 139 and the first and second upper insulatinglayers 173 and 180. The third peripheral lower contact plug 184 e is incontact with and electrically connected to the third peripheral pad 108p 3 of the peripheral wiring 180 w, and extends upwardly to penetratethrough the intermediate insulating layer 127 and the capping insulatinglayer 139 and the first and second upper insulating layers 173 and 180.The fourth peripheral lower contact plug 184 f is in contact with andelectrically connected to the upper horizontal connection layer 124 ofthe pattern structure 112 and the pattern layer 115, and extendsupwardly to penetrate through the capping insulating layer 139 and thefirst and second upper insulating layers 173 and 180.

In an example, the memory device 10 may further include a gateconnection wiring 196 b electrically connected to the gate peripheralcontact structures 192 c and the second peripheral contact structure 192d, a peripheral connection wiring 196 c electrically connected to thethird peripheral contact structure 192 e, and a source connection wiring196 d electrically connected to the fourth peripheral contact structure192 f.

The lower bit line contact plugs 184 a, the first peripheral lowercontact plug 184 b, the lower gate contact plugs 184 c, the secondperipheral lower contact plug 184 d, the third peripheral lower contactplug 184 e and the fourth peripheral lower contact plug 184 f mayinclude the same first lower plug layer 184_1, second lower plug layer184_2 and lower plug pattern 184_3.

In the lower bit line contact plugs 184 a, the first peripheral lowercontact plug 184 b, the lower gate contact plugs 184 c, the secondperipheral lower contact plug 184 d and the third peripheral lowercontact plug 184 e, the second lower plug layer 184_2 may cover a sidesurface and a bottom surface of the lower plug pattern 184_3, and thefirst lower plug layer 184_1 may cover the outer side surface and thebottom surface of the second lower plug layer 184_2.

In the case of the fourth peripheral lower contact plug 184 f, thesecond lower plug layer 184_2 may cover a side surface and a bottomsurface of the lower plug pattern 184_3, and the first lower plug layer184_1 may cover an outer side surface of the second lower plug layer184_2. The fourth peripheral lower contact plug 184 f may penetratethrough the upper horizontal connection layer 124 and may extend intothe pattern layer 115. The fourth peripheral lower contact plug 184 fmay further include a metal-semiconductor compound layer 184_4 incontact with the upper horizontal connection layer 124 and the patternlayer 115.

The first lower plug layer 184_1 may include a first metal, e.g., Ti orTa, and the second lower plug layer 184_2 may include a metal nitride,e.g., TiN, TaN, or WN, and the lower plug pattern 184_3 may include asecond metal, e.g., W. The metal-semiconductor compound layer 184_4 maybe formed of the first metal of the first lower plug layer 184_1 and asilicon compound, e.g., TiSi, TaSi, WSi, or the like. of the upperhorizontal connection layer 124 and the pattern layer 115.

In an example, the memory device 10 may be electrically connected to theconnection structure 70 described with reference to FIG. 1 through thethird peripheral contact plug 19 e and the peripheral connection wiring96 e. In the memory device 10 of FIG. 1, a connection line 55 connectingthe connection structure 70 and the peripheral circuit area 40 may bethe third peripheral contact plug 19 e and the peripheral connectionwiring 96 e.

Next, with reference to FIG. 3, the stacked structure 130 s and thevertical structure 142 in the memory cell array area 20 will bedescribed. FIG. 3 is a partially enlarged view of portion “B” in FIG.2B.

Referring to FIGS. 2B and 3, each of the horizontal layers 137 mayinclude a gate conductive material. In an example, each of thehorizontal layers 137 may include a first layer 137_1 and a second layer137_2. The first layer 137_1 may extend to between the verticalstructure 142 and a side surface of the second layer 137_2 whilecovering the upper and lower surfaces of the second layer 137_2.

In an example, the first layer 137_1 may include a dielectric material,and the second layer 137_2 may include a conductive material. Forexample, the first layer 137_1 may include a high-k dielectric, e.g.,AlO or the like, and the second layer 137_2 may include a conductivematerial, e.g., TiN, TaN, WN, TiSi, WSi, TaSi, Ti, W, or the like. Inanother example, the first layer 137_1 may include a first conductivematerial, e.g., TiN, TaN, WN, etc., and the second layer 137_2 mayinclude a second conductive material, e.g., Ti, Ta, W, or the like,different from the first conductive material.

In another example, each of the horizontal layers 137 may also be formedof a single conductive material layer without distinction between thefirst layer 137_1 and the second layer 137_2. For example, each of thehorizontal layers 137 may be formed of doped polysilicon, ametal-semiconductor compound, e.g., TiSi, TaSi, CoSi, NiSi or WSi, ametal nitride, e.g., TiN, TaN or WN, or a metal e.g., Ti, Ta, or W.

In each of the horizontal layers 137, a portion formed of a conductivematerial, e.g., the second layer 137_2, may be referred to as a gateelectrode, a gate line, or a gate layer. In an example, the horizontallayers 137 may include first and second lower gate layers 137L1 and137L2, intermediate gate layers 137M above the first and second lowergate layers 137L1 and 137L2, and first and second upper gate layers137U1 and 137U2 above the intermediate gate layers 137M.

The first and second lower gate layers 137L1 and 137L2 may correspond tothe first and second lower gate lines LL1 and LL2 described withreference to FIG. 1, and at least some of the intermediate gate layers137M may correspond to the word lines WL described with reference toFIG. 1, and the first and second upper gate layers 137U1 and 137U2 maycorrespond to the first and second upper gate lines UL1 and UL2described with reference to FIG. 1.

The vertical structure 142 may be disposed in the channel hole 140penetrating through the stacked structure 130 s and extending into thepattern structure 112. In the vertical structure 142, the dielectricstructure 144 may include a first dielectric layer 146, a data storagelayer 148 and a second dielectric layer 150. The first dielectric layer146 may conformally cover the inner wall of the channel hole 140, andthe data storage layer 148 may be disposed between the first dielectriclayer 146 and the second dielectric layer 150, and the second dielectriclayer 150 may contact the channel layer 153.

In an example, the data storage layer 148 may include regions in whichinformation may be stored in a memory device such as a NAND flash memorydevice. For example, the data storage layer 148 stores areas which maystore information, between the channel layer 153 and the intermediategate layers 137M, which may be the word lines (WL in FIG. 1) among thehorizontal layers 137. The data storage layer 148 may be formed of amaterial capable of storing information by trapping charges in a flashmemory device. The data storage layer 148 may be formed of, e.g.,silicon nitride. In an example embodiment, the silicon nitride of thedata storage layer 148 may be replaced with another material capable ofstoring information.

In an example, the channel layer 153 may include a first channel region153 a and a second channel region 153 b. The first channel region 153 amay be an undoped region, and the second channel region 153 b may be adoped region having N-type conductivity. The channel layer 153 may beformed of, e.g., a silicon layer. The first channel region 153 a may belocated below the second channel region 153 b.

The first channel region 153 a may at least face the intermediate gatelayers 137M, and the second channel region 153 b may at least face thesecond upper gate layer 137U2. In an example, the first upper gate layer137U1 may face the first channel region 153 a.

Next, referring to FIG. 4, the pad pattern 160 of the vertical structure142, the lower bit line contact plug 184 a, the upper bit line contactplug 188 a, and the conductive line 196 a will be described. FIG. 4 is apartially enlarged view of portion “C” in FIG. 3.

Referring to FIG. 4, the pad pattern 160 may include a pad metal pattern170 on the core region 156, a pad barrier layer 168 in contact with aside surface and a bottom surface of the pad metal pattern 170, and apad metal-semiconductor compound layer 166 in contact with the padbarrier layer 168. The core region 156 may be formed of an insulatingmaterial, e.g., silicon oxide.

In an example, the pad pattern 160 may further include a pad metal layer164 disposed between the pad barrier layer 168 and the core region 156.The pad metal-semiconductor compound layer 166 may be disposed betweenthe second channel region 153 b of the channel layer 153 and the padbarrier layer 168.

In an example, the pad metal layer 164 may be formed of a metal capableof forming the pad metal-semiconductor compound layer 166. For example,the pad metal layer 164 may include a metal, e.g., Ti, Ta, or W, and thepad metal-semiconductor compound layer 166 may be formed of a compoundof a metal material, e.g., Ti, Ta, or W, and a semiconductor material,e.g., Si, Ge or SiGe. For example, the pad metal-semiconductor compoundlayer 166 may be, e.g., TiSi, TiGe, or TiSiGe layer.

In an example, the pad barrier layer 168 may include a metal nitride,e.g., TiN, TaN, or WN, and the pad metal pattern 170 may include ametal, e.g., W, etc.

In an example, the pad pattern 160, the channel layer 153, and thedielectric structure 144 may have upper surfaces positioned atsubstantially the same height level.

The lower bit line contact plug 184 a may include the first lower pluglayer 184_1, the second lower plug layer 184_2, and the lower plugpattern 184_3, as described with reference to FIGS. 2B and 2C. The firstlower plug layer 184_1 of the lower bit line contact plug 184 a maycontact the pad pattern 160.

In an example, a portion of the upper surface of the lower bit linecontact plug 184 a contacts the third upper insulating layer 186, andthe rest of the upper surface of the lower bit line contact plug 184 amay contact the upper bit line contact plug 188 a. The upper bit linecontact plug 188 a may contact a portion of a side surface of the lowerbit line contact plug 184 a.

The upper bit line contact plug 188 a may be formed of the same materialas the first peripheral upper contact plug 188 b, the upper gate contactplug 188 c, the second peripheral upper contact plug 188 d, the thirdperipheral upper contact plug 188 e, and the fourth peripheral uppercontact plug 188 f as described above. For example, the upper bit linecontact plug 188 a may include an upper barrier layer 188_1 includingmetal nitride, e.g., TiN, etc., and an upper plug pattern 188_2including a metal, e.g., W, etc. The upper barrier layer 188_1 may covera side surface and a bottom surface of the upper plug pattern 188_2.

The conductive line 196 a, e.g., the bit line, may be formed of the samematerial as the gate connection wiring 196 b, the peripheral connectionwiring 196 c, and the source connection wiring 196 d described withreference to FIG. 2B. For example, the bit line 196 a may include abarrier layer 196_1 including a metal nitride, e.g., TiN, etc., and awiring pattern 196_2 including a metal, e.g., Cu, etc. The barrier layer196_1 may cover a side surface and a bottom surface of the wiringpattern 196_2.

In an example, the pad metal pattern 170, the lower plug pattern 184_3,and the upper plug pattern 188_2 may include the same first metal, e.g.,W, etc., and the wiring pattern 188_2 may include a second metal, e.g.,Cu, different from the first metal.

Next, referring to FIG. 5, an example in which a plurality of the bitlines 196 a are disposed, and planar shapes of the vertical structures142 adjacent to each other, the lower bit line contact plugs 184 a andthe upper bit line contact plugs 188 a, disposed on the verticalstructures 142, respectively, will be described.

Referring to FIG. 5, the bit lines 196 a may include a pair of first andsecond bit lines 196 a_1 and 196 a_2 parallel to each other. Each of thebit lines 196 a may extend in the Y direction. The vertical structures142 may include a pair of first and second vertical structures 142_1 and142_2 adjacent to each other in the Y direction.

The lower bit line contact plugs 184 a may include a first lower bitline contact plug 184 a_1 overlapping the first vertical structure142_1, and a second lower bit line contact plug 184 a_2 overlapping thesecond vertical structure 142_2. The upper bit line contact plugs 188 amay include a first upper bit line contact plug 188 a_1 overlapping thefirst lower bit line contact plug 184 a_1, and a second upper bit linecontact plug 188 a_2 overlapping the second lower bit line contact plug184 a_2. The first bit line 196 a_1 may overlap the first upper bit linecontact plug 188 a_1, and the second bit line 196 a_2 may overlap thesecond upper bit line contact plug 188 a_2. In an example, a width ofeach of the lower bit line contact plugs 184 a may be less than a widthof each of the vertical structures 142.

In an example, each of the upper bit line contact plugs 188 a may have arectangular or elliptical shape having a first length in the Y directionand a second length (or a width) less than the first length in the Xdirection. In an example, in each of the upper bit line contact plugs188 a, the length in the Y direction may be greater than a width of eachof the lower bit line contact plugs 184 a, and the length in the Xdirection may be less than the width of each of the lower bit linecontact plugs 184 a.

Next, a modified example of the lower bit line contact plug 184 a inFIG. 4 will be described with reference to FIG. 6. FIG. 6 is a partiallyenlarged view corresponding to the partially enlarged view of FIG. 4.

In a modified example, referring to FIG. 6, the lower bit line contactplug 184 a in FIG. 4 may be replaced with a lower bit line contact plug184 a′ overlapping the pad metal pattern 170 and the channel layer 153positioned on one side of the pad metal pattern 170. The lower bit linecontact plug 184 a′ may further include a lower extension portion 184 pextending into the channel layer 153, in a portion overlapping thechannel layer 153. The lower bit line contact plug 184 a′ may be spacedapart from the dielectric structure 144.

Next, various modified examples of the pad pattern 160 described withreference to FIG. 4 will be described with reference to FIGS. 7A to 7E.FIGS. 7A to 7E are partially enlarged views respectively correspondingto the partially enlarged view of FIG. 4. Hereinafter, in the padpatterns in the modified examples described with reference to FIGS. 7Ato 7E, the same reference numerals or the same terms as those of theconstituent elements of the pad pattern 160 described with reference toFIG. 4 refer to the same material as the constituent elements of the padpattern 160 may be the same material as the constituent elements of thepad pattern 160 described with reference to FIG. 4. Accordingly,detailed descriptions of the same reference numerals or terms as thoseof the components of the pad pattern 160 described with reference toFIG. 4 will be omitted.

In a modified example, referring to FIG. 7A, the pad pattern 160 in FIG.4 may be replaced with a pad pattern 160 a in FIG. 7A. The pad pattern160 a may include a pad metal pattern 170, a pad semiconductor layer 162covering side and bottom surfaces of the pad metal pattern 170, a padbarrier layer 168 disposed between the pad semiconductor layer 162 andthe pad metal pattern 170, and a pad metal-semiconductor compound layer166 between the pad barrier layer 168 and the pad semiconductor layer162. A semiconductor layer 162 and 153 may include the pad semiconductorlayer 162 and the channel layer 153. The pad semiconductor layer 162 mayinclude a first portion contacting the channel layer 153 and a secondportion contacting the core region 156. For example, the first portionof the pad semiconductor layer 162 may contact the second channel region153 b of the channel layer 153. The second channel region 153 b may be adoped region having N-type conductivity.

In an example, the pad semiconductor layer 162 may have a sameconductivity type as the second channel region 153 b. For example, thepad semiconductor layer 162 may have N-type conductivity. In an example,the pad semiconductor layer 162 may include at least one of, e.g., a Silayer, a Ge layer, and a SiGe layer.

In a modified example, referring to FIG. 7B, the pad pattern 160 in FIG.4 may be replaced with a pad pattern 160 b in FIG. 7B. The pad pattern160 b may include a pad metal pattern 170, a pad semiconductor layer 162covering side and bottom surfaces of the pad metal pattern 170, a padbarrier layer 168 disposed between the pad semiconductor layer 162 andthe pad metal pattern 170, and a pad metal-semiconductor compound layer166 between the pad barrier layer 168 and the pad semiconductor layer162.

In the pad pattern 160 b, the pad metal pattern 170 may include a firstwidth portion W1, and a second width portion W2 having a width greaterthan the first width portion W1 on the first width portion W1. In thepad pattern 160 b, a vertical length of the first width portion W1 maybe less than a vertical length of the second width portion W2.

An upper surface of the dielectric structure 144 and an upper surface153 e 1 of the channel layer 153 may contact the pad pattern 160 b. Anupper surface 148 e 1 of the data storage layer 148 and the uppersurface 153 e 1 of the channel layer 153 may be positioned at a lowerlevel than the upper surface of the pad pattern 160 b.

In a modified example, referring to FIG. 7C, the pad pattern 160 b ofFIG. 7B may be replaced with a pad pattern 160 c of FIG. 7C. The padpattern 160 c may include a pad metal pattern 170, a pad semiconductorlayer 162 covering side and bottom surfaces of the pad metal pattern170, a pad barrier layer 168 disposed between the pad semiconductorlayer 162 and the pad metal pattern 170, and a pad metal-semiconductorcompound layer 166 between the pad barrier layer 168 and the padsemiconductor layer 162.

In the pad pattern 160 c, the pad metal pattern 170 may include a firstwidth portion W1, a second width portion W2 having a width greater thana width of the first width portion W1 on the first width portion W1, anda third width portion W3 between the first width portion W1 and thesecond width portion W2. The third width portion W3 may have a widthgreater than the first width portion W1 and less than the second widthportion W2.

A side surface of the second width portion W2 may be inclined, and aside surface of at least one of the first width portion W1 and the thirdwidth portion W3 may be substantially vertical. Accordingly, a sidesurface of the second width portion W2 and a side surface of at leastone of the first width portion W1 and the third width portion W3 mayhave different inclinations.

The upper surface of the dielectric structure 144 and the upper surface153 e 1 of the channel layer 153 may contact the pad pattern 160 c. Theupper surface 148 e 1 of the data storage layer 148 and the uppersurface 153 e 1 of the channel layer 153 may be positioned at a lowerlevel than the upper surface of the pad pattern 160 b. The upper surface153 e 1 of the channel layer 153 may be positioned at a lower level thanthe upper surface 148 e 1 of the data storage layer 148. In the padpattern 160 c, the pad semiconductor layer 162 may contact the uppersurface 153 e 1 of the channel layer 153, and may contact a portion ofan inner side surface of the dielectric structure 144 and an uppersurface of the dielectric structure 144.

In a modified example, referring to FIG. 7D, the pad pattern 160 c ofFIG. 7C may be replaced with a pad pattern 160 d of FIG. 7D. The secondwidth portion W2 having an inclined side surface in FIG. 7C may bereplaced with a second width portion W2′ having a substantially verticalside surface as in FIG. 7D. Accordingly, the pad pattern 160 d may havea second width portion W2′.

In the pad pattern 160 d, the second width portion W2′ may have aconstant thickness T. The thickness T of the second width portion W2′may be greater than the thickness of the channel layer 153 or thethickness of the data storage layer 148. The thickness T of the secondwidth portion W2′ may be greater than the thickness of the dielectricstructure 144.

In a modified example, referring to FIG. 7E, the pad pattern 160 d inFIG. 7D may be replaced with a pad pattern 160 e in FIG. 7E. The padpattern 160 e may include a pad metal pattern 170, a pad barrier layer168 covering side and bottom surfaces of the pad metal pattern 170, apad metal-semiconductor compound layer 166 between the pad barrier layer168 and the channel layer 153, a first pad metal layer 164_1 between thepad barrier layer 168 and the core region 156, and a second pad metallayer 164_2 extending from an upper end of the pad metal-semiconductorcompound layer 166 to cover a side surface of the pad barrier layer 168.

The first and second pad metal layers 164_1 and 164_2 may be formed ofthe same material as the pad metal layer 164 described with reference toFIG. 4. The upper surface 153 e 3 of the channel layer 153 may contactthe pad metal-semiconductor compound layer 166, and the upper surface ofthe dielectric structure 144 may contact the second pad metal layer164_2.

In the pad pattern 160 e, the pad metal pattern 170 may include a firstwidth portion W1, a second width portion W2′ and a third width portionW3, having a size relationship similar to that of the pad metal pattern170 in FIG. 7D.

Next, a modified example of the pad pattern 160 and the lower bit linecontact plug 184 a described with reference to FIG. 4 will be describedwith reference to FIG. 8.

In a modified example, referring to FIG. 8, the pad pattern 160described with reference to FIG. 4 may be replaced with a pad pattern160 f as in FIG. 8. The pad pattern 160 f may be formed of a padsemiconductor layer having N-type conductivity. The lower bit linecontact plug 184 a described with reference to FIG. 4 may be replacedwith a lower bit line contact plug 184 a′ as illustrated in FIG. 8.

The lower bit line contact plug 184 a′ may further include ametal-semiconductor compound layer 184_4, compared with the lower bitline contact plug 184 a illustrated in FIG. 4. For example, the lowerbit line contact plug 184 a′ may further include the lower plug pattern184_3, a second lower plug layer 184_2 covering side and bottom surfacesof the lower plug pattern 184_3, a first lower plug layer 184_1 on anouter side surface of the second lower plug layer 184_2, and themetal-semiconductor compound layer 184_4 extending from the first lowerplug layer 184_1 and disposed between the second lower plug layer 184_2and the pad pattern 160 f. The lower bit line contact plug 184 a′ mayextend into the pad pattern 160 f.

Again, referring to FIG. 2A, the separation structure 178 may have alinear shape extending in the X direction. Hereinafter, across-sectional structure in which the separation structure 178 is cutin the X direction will be described with reference to FIG. 9. FIG. 9illustrates a cross-sectional structure of the separation structure 178cut in the X direction.

Referring to FIGS. 2A and 9, an end portion of the separation structure178 may be disposed on the pattern layer 115. In the separationstructure 178, the second separation pattern 178_2 may be formed of aconductive material. The intermediate structure 120 and the upperhorizontal connection layer 124 may be disposed on the pattern layer 115that does not overlap the separation structure 178. The intermediatestructure 120 may be spaced apart from the separation structure 178. Theperipheral wiring 108 w of the peripheral circuit 108 may furtherinclude a fourth peripheral pad 108 p 4.

In an example, the memory device 10 may further include a fifthperipheral contact structure 192 h. The fifth peripheral contactstructure 192 h may include a fifth peripheral lower contact plug 184 hand a fifth peripheral upper contact plug 188 h that are sequentiallystacked.

The fifth peripheral lower contact plug 184 h is in contact with andelectrically connected to the fourth peripheral pad 108 p 4, and extendsupward to penetrate through the intermediate insulating layer 127, thecapping insulating layer 139, and the first and second upper insulatinglayers 173 and 708.

The fifth peripheral lower contact plug 184 h may be formed ofsubstantially the same structure and material as the third peripherallower contact plug (184 e in FIG. 2B), and the fifth peripheral uppercontact plug 188 h may be formed of substantially the same structure andthe same material as the third peripheral upper contact plug (188 e inFIG. 2B).

In an example, the memory device 10 may further include a sixthperipheral upper contact plug 188 g that is in contact with andelectrically connected to the second separation pattern 178_2, on theseparation structure 178. The sixth peripheral upper contact plug 188 gmay be formed of the same material as the fifth peripheral upper contactplug 188 h.

In an example, the memory device 10 may further include a connectionwiring 196 e that is in contact with and electrically connected to thesixth peripheral upper contact plug 188 g and the fifth peripheral uppercontact plug 188 h. The connection wiring 196 e may be formed of thesame structure and material as the bit line 196 a at the same heightlevel as the bit line 196 a.

Next, an example of a method of forming a memory device according to anexample embodiment will be described with reference to FIGS. 10A to 13B.In FIGS. 10A to 13B, FIGS. 10A, 11A, 12A and 13A are cross-sectionalviews illustrating stages in a method of forming the cross-sectionalstructure of FIG. 2A, and FIGS. 10B, 11B, 12B and 13B arecross-sectional views illustrating stages in a method of forming across-sectional structure of FIG. 2B, and FIG. 10C is a partiallyenlarged view of portion “B′” in FIG. 10B. Accordingly, in thefollowing, descriptions overlapping with the content described withreference to FIGS. 2A and 2B will be omitted, and a schematic method offorming the cross-sectional structure of FIGS. 2A and 2B will bedescribed.

Referring to FIGS. 10A, 10B and 10C, a lower structure 102 may beformed.

Forming the lower structure 102 may include preparing a substrate 104and forming a peripheral circuit 108 and a lower insulating layer 110 onthe substrate 104. The peripheral circuit 108 may include a peripheralgate 108 g, a peripheral source/drain 108 s, and a peripheral wiring 108w as described with reference to FIG. 2A. The lower insulating layer 110may cover the peripheral circuit 108.

Forming the lower structure 102 may include forming a pattern structure112 having a first opening 115 a and a second opening 115 b on the lowerinsulating layer 110, forming an insulating layer, and planarizing theinsulating layer. The planarized insulating layer may be formed of afirst gap-fill insulating layer 127 g 1 remaining in the first opening115 a, a second gap-fill insulating layer 127 g 2 remaining in thesecond opening 115 b, and an intermediate insulating layer 127 remainingon an outer side surface of the pattern structure 112.

Forming the pattern structure 112 may include forming a pattern layer115, forming an intermediate layer 119 having an opening, on the patternlayer 115, forming an upper horizontal connection layer 124 filling theopening and covering the intermediate layer 119, and forming the firstand second openings 115 a and 115 b by patterning the pattern layer 115,the intermediate layer 119 and the upper horizontal connection layer124. The intermediate layer 119 may include a first layer 120 a 1, asecond layer 120 a 2, and a third layer 120 a 3 sequentially stacked.The intermediate layer 119 and the upper horizontal connection layer 124may constitute a horizontal connection layer 118.

A preliminary stacked structure 130 may be formed on the lower structure102. Forming the preliminary stacked structure 130 includes forminginterlayer insulating layers 133 and preliminary horizontal layers 136,which are alternately and repeatedly stacked, and patterning theinterlayer insulating layers 133 and the preliminary horizontal layers136, thereby forming a stepped structure in the gate connection area 30as described with reference to FIG. 2B. Subsequently, an insulatinglayer may be formed and the insulating layer may be planarized, therebyforming a capping insulating layer 139 having an upper surface coplanarwith an uppermost interlayer insulating layer 133U among the interlayerinsulating layers 133. The preliminary horizontal layers 136 may beformed of an insulating material, e.g., silicon nitride.

In the memory cell array area 20 as described with reference to FIGS. 2Aand 2B, a vertical structure 142′ that penetrates through thepreliminary stacked structure 130 and extends into the pattern structure112 may be formed. Forming the vertical structure 142′ may include, inthe memory cell array area 20, forming a channel hole extending into thepattern layer 115 while penetrating through the preliminary stackedstructure 130, the upper horizontal connection layer 124, and theintermediate layer 119, forming a dielectric structure 144 conformallycovering the inner wall of the channel hole, forming a conformal channellayer 153 on the dielectric structure 144, forming a core region 156partially filling the channel hole, and forming a pad pattern 160filling the remaining portion of the channel hole, on the core region156. The pad pattern 160 may have the same structure as the structuredescribed with reference to FIG. 5. In another example, the pad pattern160 may have the same structure as any one of the pad patterns describedwith reference to FIGS. 7A to 7E and 8.

Referring to FIGS. 11A and 11B, a first upper insulating layer 173 maybe formed on the preliminary stacked structure (130 of FIGS. 10A and10B) and the capping insulating layer 139.

A trench 176 is formed to penetrate through the first upper insulatinglayer 173 and the preliminary stacked structure (130 of FIGS. 10A and10B) and through the upper horizontal connection layer 124 and theintermediate layer (see FIGS. 10A and 10B), and is formed to extend intothe pattern layer 115. The intermediate layer (FIGS. 10A and 10B) in thememory cell array area 20 is removed to form an opening exposing theside surface of the vertical structure (142′ in FIGS. 10A and 10B), andthe dielectric structure 144 of the vertical structure (142′ in FIGS.10A and 10B) exposed by the opening is etched to expose the channellayer 153, and a lower horizontal connection layer 122 filling theopening may be formed. Accordingly, the vertical structure 142 asdescribed in FIGS. 2A and 2B may be formed.

After forming the lower horizontal connection layer 122, the preliminaryhorizontal layers 136 of the preliminary stacked structure (130 of FIGS.10A and 10B) exposed by the trench 176 are partially etched to form anopening exposing a side surface of the vertical structure 142, andhorizontal layers 137 filling the opening may be formed. The horizontallayers 137 may be the same as the horizontal layers described withreference to FIGS. 2A, 2B and 3. Accordingly, a stacked structure 130 sincluding the horizontal layers 137 and the interlayer insulating layers133 may be formed.

Portions of the preliminary horizontal layers 136 of the preliminarystacked structure (130 in FIGS. 10A and 10B) remain to form theinsulating layers 136 a of the first and second insulating regions 130i_1 and 130 i_2 as described with reference to FIGS. 2A and 2B.Subsequently, a separation structure 178 filling the trench 176 may beformed. Forming the separation structure 178 may include forming a firstseparation pattern 178_1 on a side surface of the trench 176 and forminga second separation pattern 178_2 filling the trench 176.

Referring to FIGS. 12A and 12B, a second upper insulating layer 180 maybe formed on the first upper insulating layer 173. A lower bit linecontact hole 182 a, a first peripheral lower contact hole 182 b, a lowergate contact hole 182 c, a second peripheral lower contact hole 182 d, athird peripheral lower contact hole 182 e and a fourth peripheral lowercontact hole 182 f may be formed simultaneously with each other.

The lower bit line contact hole 182 a may penetrate through the firstand second upper insulating layers 173 and 180 and expose the padpattern 160 of the vertical structure 142.

The first peripheral lower contact hole 182 b may penetrate through thefirst and second upper insulating layers 173 and 180, the firstinsulating region 130 i_1, and the first gap-fill insulating layer 127 g1, and may extend into the lower insulating layer 110, and may expose afirst peripheral pad 108 p 1 of the peripheral wiring 108 w. The lowergate contact hole 182 c may penetrate through the capping insulatinglayer 139 and the first and second upper insulating layers 173 and 180and may expose gate pads GP of the horizontal layers 137. The secondperipheral lower contact hole 182 d may penetrate through the secondinsulating region 130 i_2, the capping insulating layer 139, and thefirst and second upper insulating layers 173 and 180, and may expose asecond peripheral pad 108 p 2 of the peripheral wiring 180 w. The thirdperipheral lower contact hole 182 e may penetrate through theintermediate insulating layer 127, the capping insulating layer 139, andthe first and second upper insulating layers 173 and 180, and may exposea third peripheral pad 108 p 3 of the peripheral wiring 180 w. Thefourth peripheral lower contact hole 182 f may penetrate through thecapping insulating layer 139 and the first and second upper insulatinglayers 173 and 180, and may expose the pattern layer 115 and the upperhorizontal connection layer 124 of the pattern structure 112.

The pad pattern 160 may include the pad metal pattern (170 in FIG. 4).Therefore, by forming the pad metal pattern (170 in FIG. 4) formed of ametal, damage to the channel layer 153 and the dielectric structure 144may be prevented while the first peripheral lower contact hole 182 b,the lower gate contact hole 182 c, the second peripheral lower contacthole 182 d, the third peripheral lower contact hole 182 e and the fourthperipheral lower contact hole 182 f are formed. Accordingly, the lowerbit line contact hole 182 a is formed simultaneously with the formationof the first peripheral lower contact hole 182 b, the lower gate contacthole 182 c, the second peripheral lower contact hole 182 d, the thirdperipheral lower contact hole 182 e and the fourth peripheral lowercontact hole 182 f, thereby increasing productivity.

In an example, while forming the lower bit line contact hole 182 a withthe first peripheral lower contact hole 182 b, the lower gate contacthole 182 c, the second peripheral lower contact hole 182 d, the thirdperipheral lower contact hole 182 e and the fourth peripheral lowercontact hole 182 f; an alignment key may be formed in a scribe lane areasimultaneously.

Referring to FIGS. 13A and 13B, a process of simultaneously filling thelower bit line contact hole 182 a, the first peripheral lower contacthole 182 b, the lower gate contact hole 182 c, the second peripherallower contact hole 182 d, the third peripheral lower contact hole 182 eand the fourth peripheral lower contact hole 182 f, with a conductivematerial, may be performed. Accordingly, the lower bit line contactplugs 184 a, the first peripheral lower contact plug 184 b, the lowergate contact plugs 184 c, the second peripheral lower contact plug 184d, the third peripheral lower contact plug 184 e, and the fourthperipheral lower contact plug 184 f may be formed to fill the lower bitline contact hole 182 a, the first peripheral lower contact hole 182 b,the lower gate contact hole 182 c, the second peripheral lower contacthole 182 d, and the third peripheral lower contact hole 182 e and thefourth peripheral lower contact hole 182 f, respectively. Accordingly,the lower bit line contact plugs 184 a, the first peripheral lowercontact plug 184 b, the lower gate contact plugs 184 c, the secondperipheral lower contact plug 184 d, and the third peripheral lowercontact plug 184 e and the fourth peripheral lower contact plug 184 fmay be simultaneously formed, thereby improving productivity.

Subsequently, referring to FIGS. 2A and 2B, a third upper insulatinglayer 183 may be formed on the second upper insulating layer 180. Theupper bit line contact plug 188 a, the first peripheral upper contactplug 188 b, the upper gate contact plug 188 c, the second peripheralupper contact plug 188 d, the third peripheral upper contact plug 188 e,and the fourth peripheral upper contact plug 188 f may be simultaneouslyformed to penetrate through the third upper insulating layer 183.Subsequently, a fourth upper insulating layer 194 may be formed on thethird upper insulating layer 183. The bit line 196 a, the gateconnection wiring 196 b, the peripheral connection wiring 196 c, and thesource connection wiring 196 d may be simultaneously formed to penetratethrough the fourth upper insulating layer 194.

Next, a modified example of a method of forming a memory deviceaccording to an example embodiment will be described with reference toFIGS. 14A to 15B. In FIGS. 14A to 15B, FIGS. 14A and 15A arecross-sectional views illustrating a method of forming thecross-sectional structure of FIG. 2A, and FIGS. 14B and 15B arecross-sectional views illustrating a method of forming thecross-sectional structure of FIG. 2B.

Referring to FIGS. 14A and 14B, a second upper insulating layer 180 maybe formed on the result described with reference to FIGS. 11A and 11B. Afirst mask pattern 193 a may be formed on the second upper insulatinglayer 180. An etching process in which the first mask pattern 193 a isused as an etching mask may be performed to form a lower bit linecontact hole 182 a. The lower bit line contact hole 182 a may penetratethrough the first and second upper insulating layers 173 and 180 andexpose the pad pattern 160 of the vertical structure 142.

In an example, while forming the lower bit line contact hole 182 a, analignment key may be simultaneously formed in the scribe lane area.

Referring to FIGS. 15A and 15B, after removing the first mask pattern193 a, a second mask pattern 193 b may be formed. By performing anetching process using the second mask pattern 193 b as an etching mask,the first peripheral lower contact hole 182 b, the lower gate contacthole 182 c, the second peripheral lower contact hole 182 d, the thirdperipheral lower contact hole 182 e, and the fourth peripheral lowercontact hole 182 f, as described with reference to FIGS. 12A and 12B,may be simultaneously formed. Subsequently, the second mask pattern 193b may be removed. Thus, the same result as in FIGS. 12A and 12B may beformed. Subsequently, as described with reference to FIGS. 13 and 13B,the lower bit line contact plugs 184 a, the first peripheral lowercontact plug 184 b, the lower gate contact plugs 184 c, the secondperipheral lower contact plug 184 d, the third peripheral lower contactplug 184 e, and the fourth peripheral lower contact plug 184 f may besimultaneously formed.

According to example embodiments, by providing a method ofsimultaneously forming the lower bit line contact plugs 184 a, the firstperipheral lower contact plug 184 b, the lower gate contact plugs 184 c,the second peripheral lower contact plug 184 d, the third peripherallower contact plug 184 e and the fourth peripheral lower contact plug184 f, productivity may be improved.

According to example embodiments, the lower bit line contact plugs 184a, the first peripheral lower contact plug 184 b, the lower gate contactplugs 184 c, the second peripheral lower contact plug 184 d, the thirdperipheral lower contact plug 184 e and the fourth peripheral lowercontact plug 184 f are simultaneously formed, and a pad pattern 160including the pad metal pattern 170 formed of a metal material may alsobe provided to prevent etching damage to the channel layer 153 and thedielectric structure 144. Therefore, the productivity and reliability ofthe memory device 10 may be improved. By forming the pad metal pattern170 of a metal material, electrical characteristics of the memory device10 may be improved.

By way of summation and review, example embodiments provide a memorydevice in which the integration thereof may be improved. Exampleembodiments provide a memory device in which productivity andreliability may be improved.

That is, as set forth above, according to example embodiments, byproviding a method of simultaneously forming lower bit line contactplugs, peripheral lower contact plugs, and lower gate contact plugs,productivity may be improved. To simultaneously form lower bit linecontact plugs, lower peripheral contact plugs, and lower gate contactplugs, and to prevent etching damage to a dielectric structure and achannel layer of a vertical structure, a pad pattern including a padmetal pattern formed of a metal material may be provided. Accordingly,the productivity and reliability of a memory device may be improved. Asthe pad metal pattern is formed of a metal material, electricalcharacteristics of the memory device may be improved.

Example embodiments have been disclosed herein, and although specificterms are employed, they are used and are to be interpreted in a genericand descriptive sense only and not for purpose of limitation. In someinstances, as would be apparent to one of ordinary skill in the art asof the filing of the present application, features, characteristics,and/or elements described in connection with a particular embodiment maybe used singly or in combination with features, characteristics, and/orelements described in connection with other embodiments unless otherwisespecifically indicated. Accordingly, it will be understood by those ofskill in the art that various changes in form and details may be madewithout departing from the spirit and scope of the present invention asset forth in the following claims.

What is claimed is:
 1. A memory device, comprising: a lower structure; astacked structure on the lower structure, the stacked structureincluding horizontal layers and interlayer insulating layers alternatelystacked in a vertical direction, and each of the horizontal layersincluding a gate electrode; a vertical structure penetrating through thestacked structure in the vertical direction, the vertical structureincluding: a core region, a pad pattern including a pad metal pattern onthe core region, a dielectric structure including a first portion facinga side surface of the core region, a second portion facing at least aportion of a side surface of the pad metal pattern, and a data storagelayer, and a channel layer between the dielectric structure and the coreregion; a contact structure on the vertical structure; and a conductiveline on the contact structure.
 2. The memory device as claimed in claim1, wherein the channel layer extends between the second portion of thedielectric structure and the side surface of the pad metal pattern, andbetween the first portion of the dielectric structure and the coreregion.
 3. The memory device as claimed in claim 1, wherein the padpattern further includes: a pad barrier layer in contact with the sidesurface of the pad metal pattern and a bottom surface of the pad metalpattern; and a pad metal-semiconductor compound layer in contact withthe pad barrier layer, at least a portion of the pad barrier layer beingbetween the pad metal-semiconductor compound layer and the pad metalpattern.
 4. The memory device as claimed in claim 3, wherein the padpattern further includes a first pad metal layer between the pad barrierlayer and the core region, the pad metal-semiconductor compound layerbeing between the channel layer and the pad barrier layer.
 5. The memorydevice as claimed in claim 1, wherein the pad pattern further includes apad semiconductor layer between the pad metal pattern and the coreregion and extending onto the side surface of the pad metal pattern. 6.The memory device as claimed in claim 5, wherein the pad pattern furtherincludes: a pad barrier layer covering the side surface of the pad metalpattern and a bottom surface of the pad metal pattern; and a padmetal-semiconductor compound layer between the pad barrier layer and thepad semiconductor layer.
 7. The memory device as claimed in claim 1,wherein the pad metal pattern includes: a first width portion having afirst width; and a second width portion having a second width greaterthan the first width, and wherein an upper surface of the channel layeris in contact with the pad pattern.
 8. The memory device as claimed inclaim 7, wherein an upper surface of the data storage layer is incontact with the pad pattern.
 9. The memory device as claimed in claim7, wherein the pad metal pattern further includes a third width portionhaving a third width, between the first width portion and the secondwidth portion, the third width being greater than the first width andless than the second width.
 10. The memory device as claimed in claim 1,wherein the contact structure includes: a lower contact plug in contactwith the pad pattern, the lower contact plug including: a lower plugpattern, and a lower barrier layer covering a side surface and a bottomsurface of the lower plug pattern; and an upper contact plug on thelower contact plug and contacting the lower contact plug, the uppercontact plug including: an upper plug pattern, and an upper barrierlayer covering a side surface and a bottom surface of the upper plugpattern.
 11. The memory device as claimed in claim 10, wherein the lowercontact plug further includes a lower metal layer covering a bottomsurface and an outer side surface of the lower barrier layer.
 12. Amemory device, comprising: a lower structure; a stacked structure on thelower structure, the stacked structure including gate layers andinterlayer insulating layers alternately stacked in a verticaldirection, and gate pads extending from the gate layers and arranged ina stepped shape; a first vertical structure penetrating through thestacked structure in the vertical direction, the first verticalstructure including: a core region, a dielectric structure on a sidesurface of the core region, the dielectric structure including a datastorage layer, a pad metal pattern on the core region, and asemiconductor layer facing at least a portion of a side surface of thepad metal pattern; a first contact structure on the first verticalstructure, the first contact structure including: a first lower contactplug contacting the first vertical structure, and a first upper contactplug on the first lower contact plug and contacting the first lowercontact plug; gate contact structures on the gate pads; a peripheralcontact structure spaced apart from the gate layers; a conductive lineon the first contact structure; and gate connection wirings on the gatecontact structures.
 13. The memory device as claimed in claim 12,wherein the semiconductor layer includes: a channel layer between thedielectric structure and the core region, the channel layer including anundoped region and a doped region; and a pad semiconductor layer incontact with the channel layer, the pad semiconductor layer having asame conductivity type as the doped region and contacts the dopedregion.
 14. The memory device as claimed in claim 12, wherein the firstvertical structure further includes a pad barrier layer covering theside surface of the pad metal pattern and a bottom surface of the padmetal pattern, and a metal-semiconductor compound layer between the padbarrier layer and the semiconductor layer.
 15. The memory device asclaimed in claim 12, wherein the lower structure includes: a substrate;a peripheral circuit on the substrate; a lower insulating layer coveringthe peripheral circuit; and a pattern structure with an opening on thelower insulating layer, wherein each of the gate contact structuresincludes a lower gate contact plug and an upper gate contact plug on thelower gate contact plug, wherein the peripheral contact structureincludes a peripheral lower contact plug and a peripheral upper contactplug on the peripheral lower contact plug, wherein the conductive lineand the gate connection wirings are on a same level as each other,wherein the peripheral lower contact plug, the lower gate contact plug,and the first lower contact plug have upper surfaces on a same level aseach other, and wherein a lower surface of the peripheral lower contactplug is in contact with a peripheral pad of the peripheral circuit. 16.The memory device as claimed in claim 15, further comprising: a secondvertical structure penetrating through the stacked structure in thevertical direction, the second vertical structure having a same materialand substantially a same cross-sectional structure as the first verticalstructure; and a second contact structure on the second verticalstructure and contacting the second vertical structure, the conductiveline being in contact with the first contact structure and the secondcontact structure.
 17. A system, comprising: a memory device; and acontroller device electrically connected to the memory device, thememory device including: a lower structure, a stacked structure on thelower structure, the stacked structure including gate layers andinterlayer insulating layers alternately stacked in a verticaldirection, perpendicular to an upper surface of the lower structure, andgate pads extending from the gate layers and arranged in a steppedshape, a vertical structure penetrating through the stacked structure inthe vertical direction, the vertical structure including: a core region,a dielectric structure including a data storage layer, on a side surfaceof the core region, a pad metal pattern on the core region, and asemiconductor layer facing at least a portion of a side surface of thepad metal pattern, a first contact structure on the vertical structure,the first contact structure including a first lower contact plugcontacting the vertical structure, and a first upper contact plug on thefirst lower contact plug and contacting the first lower contact plug,gate contact structures on the gate pads, a second contact structurespaced apart from the gate layers and the vertical structure, aconductive line on the first contact structure, gate connection wiringson the gate contact structures, and a peripheral connection wiring onthe second contact structure.
 18. The system as claimed in claim 17,wherein the vertical structure further includes a pad barrier layercovering a side surface of the pad metal pattern and a bottom surface ofthe pad metal pattern, and a metal-semiconductor compound layer betweenthe pad barrier layer and the semiconductor layer.
 19. The system asclaimed in claim 17, wherein the lower structure includes: a substrate;a peripheral circuit on the substrate; a lower insulating layer coveringthe peripheral circuit; and a pattern structure having an opening, onthe lower insulating layer, wherein each of the gate contact structuresincludes a lower gate contact plug and an upper gate contact plug on thelower gate contact plug, wherein the second contact structure includes asecond lower contact plug and a second upper contact plug on the secondlower contact plug, wherein the conductive line and the gate connectionwirings are on a same level, wherein the first lower contact plug, thelower gate contact plug, and the second lower contact plug have uppersurfaces on a same level as each other, wherein a lower surface of thesecond lower contact plug is in contact with a peripheral pad of theperipheral circuit, wherein the first lower contact plug, the lower gatecontact plug, and the second lower contact plug include lower plugpatterns of a same material and lower barrier layers of a same material,the lower barrier layers covering at least a side surface of the lowerplug pattern.
 20. The system as claimed in claim 19, further comprisinga connection structure electrically connecting the controller device andthe memory device, the connection structure including a printed circuitboard or a board, and the memory device being electrically connected tothe connection structure through the second contact structure and theperipheral connection wiring.